1. Field of the Invention
The present disclosure relates generally to the design and manufacture of Integrated Circuits (ICs). More specifically, the present invention relates to power saving modifications to semiconductor memory devices.
2. Description of the Related Art
In all handheld computing and communications devices, including Personal Digital Assistants (PDAs), handheld computers and cellular telephones, careful management of power usage is critical to obtain the longest possible operating time from the battery before the battery must be either recharged or replaced. Each IC in the device must be designed to minimize its operating power requirements.
A general equation commonly used to quantify power consumption in an IC is:Power=k C V2 fwhere k is a constant that depends on the average level of IC activity, C is the IC's internal capacitance, V is the IC's operating voltage and f is the operating frequency of the IC.
Many known techniques are available to minimize power consumption in an IC. Process related techniques change the physical characteristics of the IC's transistors, thereby changing their power/performance behavior. Transistors with a lower threshold voltage switch faster, but have a greater leakage current. CMOS circuits built with these lower threshold voltages have a wider range of voltages where both the N-type and P-type transistors in the circuit are ON simultaneously, which generates a wasteful current flow known as the “crowbar current.” These process techniques particularly affect the capacitance and operating voltage of the IC.
Architectural techniques, including varying the time and frequency of clock gating, address the average level of IC activity k and its operating frequency f. Circuit design techniques include reducing either the number or the size of the transistors needed to implement a given function, which reduces the capacitance of the IC. Finally, adjusting the basic electrical operating properties of the IC affects both the IC operating voltage and its operating frequency.
In most known portable devices, the microprocessors that run them and the memories that are coupled to the microprocessors to support microprocessor operation all run at a constant frequency. Although power saving methods have developed which include putting the microprocessor into a sleep mode when the device is idle, no useful processing typically occurs during these sleep modes. In order to process data, the microprocessor must be active and, in most known systems, if the microprocessor is active it operates at a single predetermined frequency.
It follows that memory coupled to and supporting the microprocessors has previously typically operated at only one speed. In the system's sleep mode, there are few or no memory accesses and the memory can be shut down completely. To allow memory to operate at different frequencies and different voltage levels, either the memory circuitry or its method of operation would have to be modifiable on demand.
Although power savings have been achieved using sleep modes, greater operational flexibility while still providing significant power saving is obviously desirable. Any decrement in memory performance occasioned by this power saving would also have to be minimized.